This disclosure relates generally to drivers in software and hardware systems and, more particularly, to more efficient drivers for software and hardware network timing systems.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Network protocols such as the Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Timing Protocol (PTP) and Network Timing Protocol (NTP) are used to synchronize different computing devices or different components of computing devices. These protocols may involve using a hardware or software driver to read timestamps after data packets arrive to a particular hardware component of a computing device or other device or after data packets depart from the particular hardware component or other device. In some instances, the arrival or departure of the data packets may be identified by the driver by an interrupt mechanism or by way of repeatedly polling a status bit as part of a direct memory access (DMA) mechanism. Further, since the associated timestamp may be useful for certain application programs running on the computing device, the driver may once again use a polling mechanism or an interrupt mechanism to fetch the timestamp from the hardware. Because the driver may depend solely upon polling mechanisms and interrupt mechanisms to fetch timestamp data, the driver may often incur delay in reading the time, and particularly more variable delay in reading the timestamp. It may be useful to provide techniques to improve delay and deterministic latency in network timing systems.